通过条件成 绩：60 分
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Unit1_Introduction to SOC_2024_v2
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Unit2_Basic Concepts and Practices of Verilig
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Questions_Unit2_Basic Concepts and Practices of Verilig
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Lab_1_PE_NCUE
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Basic concepts of Verilog_I
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Basic concepts of Verilog_II
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Unit3_RTL Coding Guidelines
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Basic concepts of Verilog_III
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Basic concepts of Verilog_IV
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Basic concepts of Verilog_V
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test18_a
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test18_b
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Unit 6_Fundamentals of AI Visual Algorithms_External
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Unit 7_AI Visual Algorithms and Implementations_Updated
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Unit 8_Modern AI Visual Computing Systems_202410
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Paper_Reading_Assignment_In_Class
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Transformer_HW_Papers
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Modern AI Accelerators_202410
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Unit4_Timing and delays in HDL
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Unit 5_Writing Testbenches
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Lab2_PE Array
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Lab3_Input Registers
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Lab 4 Pooling
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Lab 5 ReLU
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Lab 6 模組整合
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Lab7 資料傳輸設計
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Lab 整合
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2_2 PE及內部控制設計
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2_流程
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3_1高平行度之硬體控制設計
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1_神經網路原理
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2_1 vivado install
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lab2_testbench
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Lab Report Refinement
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Low_Power_Multiplier_KHCHEN_ASSCC06_Extension_Revd
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On line_T VLSI_A Low-Power Multiplier With the Spurious Power Suppression Technique
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SPST DSP_Onlone
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Modern AI Accelerators_20241230
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Falcon_A_Fused-Layer_Accelerator_With_Layer-Wise_Hybrid_Inference_Flow_for_Computational_Imaging_CNNs
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CINE_A_4K-UHD_Energy-Efficient_Computational_Imaging_Neural_Engine_With_Overlapped_Stripe_Inference_and_Structure-Sparse_Kernel
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D23-033
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D24-065
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FPGA_Demos
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